Author:
Sun Ruiyi,Zhang Yan,Cui Aijiao
Abstract
Abstract
Affine arithmetic (AA) is widely used in range analysis in word-length optimization of hardware designs. To reduce the uncertainty in the AA and achieve efficient and accurate range analysis of multiplication, this paper presents a novel refined affine approximation method, Approximation Affine based on Space Extreme Estimation (AASEE). The affine form of multiplication is divided into two parts. The first part is the approximate affine form of the operation. In the second part, the equivalent affine form of the estimated range of the difference, which is introduced by the approximation, is represented by an extra noise symbol. In AASEE, it is proven that the proposed approximate affine form is the closest to the result of multiplication based on linear geometry. The proposed equivalent affine form of AASEE is more accurate since the extreme value theory of multivariable functions is used to minimize the difference between the result of multiplication and the approximate affine form. The computational complexity of AASEE is the same as that of trivial range estimation (AATRE) and lower than that of Chebyshev approximation (AACHA). The proposed affine form of multiplication is demonstrated with polynomial approximation, B-splines, and multivariate polynomial functions. In experiments, the average of the ranges derived by AASEE is 59% and 89% of that by AATRE and AACHA, respectively. The integer bits derived by AASEE are 2 and 1 b less than that by AATRE and AACHA at most, respectively.
Publisher
Springer Science and Business Media LLC
Reference30 articles.
1. Constantinides G, Woeginger G: The complexity of multiple wordlength assignment. Appl. Math. Lett 2002, 15(2):137-140. 10.1016/S0893-9659(01)00107-0
2. Cmar R, Rijnders L, Schaumont P, Vernalde S, Bolsens I: A methodology and design environment for DSP ASIC fixed point refinement. In Proceedings of Design, Automation and Test in Europe. Munich: IEEE Computer Society; 09–12 March 1999:271-276.
3. Kum K, Sung W: Combined word-length optimization and high level synthesis of digital signal processing systems. IEEE Trans. Computer-Aided Design Integr. Circuits Syst 2001, 20(8):921-930. 10.1109/43.936374
4. Roy S, Banerjee P: An algorithm for trading off quantization error with hardware resources for MATLAB-based FPGA design. IEEE Trans. Comput 2005, 54(7):886-896. 10.1109/TC.2005.106
5. Mallik A, Sinha D, Zhou H: Low-power optimization by smart bit-width allocation in a SystmC-based ASIC design environment. IEEE Trans. Computer-Aided Design Integr. Circuits Syst 2007, 26(3):447-455.
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