1. S Mai, C Zhang, Y Zhao, J Chao, Z Wang, in Proc. International Conference on ASIC (ASICON). An application-specific memory partitioning method for low power (IEEEGuilin, China, 2007).
2. L Benini, A Macii, M Poncino, in Proc. International Symposium on Low Power Electronics and Design (ISLPED). A recursive algorithm for low power memory partitioning (IEEERapallo, Italy, 2000).
3. S Krishnamoorthy, U Catalyurek, J Nieplocha, A Rountev, P Sadayappan, in Proc. The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC). Hypergraph Partitioning for Automatic Memory Hierarchy Management (IEEETampa, FL, USA, 2006).
4. F Menichelli, M Olivieri, Static minimization of total energy consumption in memory subsystem for scratchpad-based systems-on-chips. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.17(2), 161–171 (2009).
5. S Pasricha, ND Dutt, A framework for cosynthesis of memory and communication architectures for MPSoC. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (TCAD). 26(3), 408–420 (2007).