Low-power latch comparator with accurate hysteresis control

Abstract

Abstract Recent research has focused on finding ways to control hysteresis of dynamic comparators. The current proposed techniques are based on either geometrical dimension adjustment or digital control. The first case does not allow for post fabrication control, while the second has limited accuracy. This paper presents a new dynamic comparator design with external hysteresis adjustment using an analog voltage. This is achieved by proposing an architecture including control devices with a specific sizing. This is performed with no significant increase of the design complexity, keeping the power consumption as low as possible. The design is analyzed, showing that the proposed solution allows accurate hysteresis adjustment without affecting the inherent circuit properties. The dynamic comparator is also implemented using a 180 nm commercially available CMOS technology. The results show that a variation of 550 mV of the control voltage allows an accurate hysteresis adjustment ranging from 0 to 40 mV, according to the input conditions. Moreover, the simplicity of the circuit in conjunction with the use of dynamic technology have allowed the best performances to be achieved compared to the current state of the art, in terms of energy with an FoM equal to 116 fJ/decision and silicon area of 180 µm2 .