Analysis of SMT component land pad discontinuity effect on the overall transmission line impedance in high-speed applications

Author:

Barzdenas Vaidotas1,Vasjanov Aleksandr1

Affiliation:

1. 1 Department of Computer Science and Communications Technologies , Vilnius Gediminas Technical University , Vilnius , Lithuania

Abstract

Abstract High-speed and high-frequency PCB interconnect solutions with the slightest discontinuities in the physical geometry along the microstrip transmission line can significantly degrade the integrity of the signal being transferred. This paper presents an analysis of SMT component pads and their impact on the successive transmission line impedance. During 0805, 1206 and 2512 package size SMT component pad discontinuity evaluations it was spotted, that the increasing deviation from target impedance affects the microstrip impedance segment following the discontinuity. A 25 Ω impedance offset at the SMT pad reduces the line impedance afterwards by up to 7 Ω. A 37 Ω impedance offset results in a microstrip impedance reduction by up to 15 Ω, whereas a 45 Ω impedance change leads to a reduction of successive segment impedance by up to 30 Ω. This effect is also present in multiple evenly-spaced discontinuities. But a single reference plane cut-out, which is twice as wide as the SMT component discontinuity, substantially improves the overall impedance of the transmission line, including the successive line segment impedance drop.

Publisher

Walter de Gruyter GmbH

Reference14 articles.

1. S. H. Hall, and H. L. Heck, Advanced Signal Integrity for High-Speed Digital Designs, Wiley-IEEE Press, 2009.

2. Texas Instruments, High-Speed Interface Layout Guidelines, Application Note, https://www.ti.com/lit/an/spraar7i/spraar7i.pdf, 16-Mar-2023.

3. Toradex, Layout Design Guide, https://docs.toradex.com/102492-layout-design-guide.pdf, 16-Mar-2023.

4. Renesas, RYZ024A Module Integration Guide, https://www.renesas.com/us/en/document/apn/ryz024a-module-integration-gui de, 16-Mar-2023.

5. Intel, AN 672, Transceiver Link Design Guidelines for High-Gbps Data Rate, https://www.intel.com/content/www/us/en/programmable/documentation/nik1412632494319.html, Mar-2023.

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