1. IEEE 1364-2005, Verilog Standard.
2. Bergeron, J., Writing Testbenches: Functional Verification of HDL Models, Kluwer, 2003.
3. Tool Called Formality by Synopsys, http://www.synop-sys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx ).
4. Chupilko, M. and Kamkin, A., A TLM-based Approach to Functional Verification of Hardware Components at Different Abstraction Levels, 12th Latin-American Test Workshop, 2011.
5. Clarke, E., Grumberg, O., and Peled, D., Model Checking, MIT Press, 1999.