1. Denisenko, V.V., Kompaktnye modeli MOP tranzistorov dlya SBIS. Chast’ 1. // Elektronika NTB, no. 5, 2004, pp. 76–78, chast’ 2, no. 6, pp. 60–63.
2. Wan, B. and Shi, C.-J.R., Hierarchical Multi-Dimensional Table Lookup for Model-Compiler-Based Circuit Simulation, IEE Proc.-Comput. Digit Tech, 2005, vol. 152, no. 1, pp. 39–44.
3. Wan, B. and Shi, C.-J.R., Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, vol. 2, pp. 16–20.
4. Yanilmaz, M. and Eveleigh, V., Numerical Device Modeling for Electronic Circuit Simulation, IEEE Trans. Computer-Aided Design, March, 1991, vol. 10, pp. 366–375.
5. Rofougaran, A. and Adidi, A.A., A Table Lookup FET Model for Accurate Analog Circuit Simulation, IEEE Trans. on CAD of ICAS. Febr, 1993, vol. 12, no. 2, pp. 324–335.