New CMOS circuit implementation of a one-bit full-adder cell-Reference-Cited by-同舟云学术

New CMOS circuit implementation of a one-bit full-adder cell

Published:2011-03 Issue:2 Volume:40 Page:119-127
ISSN:1063-7397
Container-title:Russian Microelectronics
language:en
Short-container-title:Russ Microelectron

Author:

Shubin V. V.

Publisher

Pleiades Publishing Ltd

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://link.springer.com/content/pdf/10.1134/S1063739711010057.pdf

Reference24 articles.

1. Rabaey, J.M., Chandrakasan, A., and Nikolic, B., Digital Integrated Circuits, A Design Perspective, Englewood Cliffs, N.J.: Prentice Hall, 2002, 2nd ed.

2. Uyemura, J., CMOS Logic Circuit Design, Kluwer, 1999.

3. Weste, N. and Eshragian, K., Principles of CMOS VLSI Design: A Systems Perspective, Addison-Wesley, 1993.

4. Zimmermann, R. and Fichtner, W., Low-Power Logic Styles: CMOS versus Pass-Transistor Logic, IEEE J. Solid-State Circuits, 1997, vol. 32, pp. 1079–1090.

5. Khatibzaden, A.A. and Raamran, K., A 14-Transistor Low-Power High-Speed Full Adder Cell, Department of Electrical and Computer Engineering Ryerson Universiry, Toronto, Ontario, Canada, M5B 2K3, CCECE 2003 — CCGEI 2003, Montreal, 2003.

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