1. Anita Angeline, A. and Kanchana Bhaaskaran, V.S., Speed enhancement techniques for clock-delayed dual keeper domino logic style, Int. J. Electron., 2020, vol. 107, no. 8, pp. 1239–1253. https://doi.org/10.1080/00207217.2020.1726486
2. Neelima, K., Mounika, P., and Mounika, V., Reddy presented a paper on “Design of single ended low power stable SRAM cell for portable Applications”, Int. Conf. on Applications of MEMS, Nano and Smart Materials (ICMNSM-2019), Tirupati: National MEMS Design Center (NMDC) & Dept. of ECE, SVEC, 2019.
3. Koppala, N. and Bharathi, M., Gated-VDD Based Single Ended SRAM Arrays, i-Manager’s J.
Circuits Syst., 2015, vol. 3, no. 2, p. 19.
4. Neelima, K. and Prasad, K.P., Design of a low power and highly stable single ended SRAM cell, i-manager’s J.
Circuits Syst., 2014, vol. 3, no. 1, pp. 28–34. https://doi.org/10.26634/jcir.3.1.3260
5. Neelima, K. and Lakshmi Narayana, K.C., Design of a novel gated 5T SRAM cell with low power dissipation in active and sleep mode, i-manager’s J.
Circuits Syst., 2014, vol. 2, no. 4, pp. 13–20. https://doi.org/10.26634/jcir.2.4.3220