Affiliation:
1. AO "Nauchno-issledovatel'skiy institut elektronnoy tehniki"
2. AO "Nauchno-issledovatel'skiy institut kosmicheskogo priborostroeniya"
3. JSC «Micron»
4. Voronezh State University of Forestry and Technologies named after G.F. Morozov
Abstract
The article discusses the important stages of the process of developing a digital device of microelectronics associated with testing and compiling models of digital blocks. The work was carried out as part of the creation of a domestic CAD system designed for the design of various digital microelectronics devices. The presented works were carried out by VSFEU together with ROSELECTRONICS Holding. The authors have developed a model of a digital microprocessor based on SYNTACORE's SCR1 core, a 32-bit fully functional RISC-V architecture model with an IMC instruction set. To simulate the RTL model, an XCELIUM simulator with a SimVision visualization shell from Cadence was used, which allows a complete analysis of the RTL model. The core model was compiled using the Genus software from the Cadence development package. Next, the model was configured and optimized according to the time parameters according to the specified restrictions on the microprocessor being developed. It is important to note that effective testing and compilation of digital block models requires the use of specialized tools, such as automated testing tools and version control systems. This makes it possible to significantly speed up the development process and improve the quality of the final product. As a result, a package of files for Innovus software was formed to create a topology.
Publisher
Infra-M Academic Publishing House
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