Hardware efficient circuit for low error logarithmic converter

Author:

Jammu Bhaskara Rao1,Harsha L. Guna Sekhar Sai1,Bodasingi Nalini2,Veeramachaneni Sreehari3,Mohammad Noor4

Affiliation:

1. Department of ECE, GVP College of Engineering (A), Visakhapatnam, India

2. Department of ECE, JNTUK UCEV, Vizianagaram, India

3. Department of ECE, GRIET, Hyderabad, India

4. Department of CSE, IIITDM Kancheepuram, Tamilnadu, India

Abstract

The need to implement high-speed Signal processing applications in which multiplication and division play a vital role made logarithmic arithmetic a prominent contender over the traditional arithmetic operations in recent years. But the logarithm and antilogarithm converters are the bottlenecks. In order to reduce the logarithmic conversion complexity, several works have been introduced from time to time for correcting the error in Mitchell’s algorithm but at the cost of hardware. In this work, we propose a 32-bit binary to the binary logarithmic converter with a simple correction circuit compared with existing techniques. Unlike the current methods that use the linear piece-wise approximation in the mantissa, we propose a weighted average method to correct the error in Mitchell’s approximation. The maximum error percentage from the proposed work is 0.91%, which is 16.9% of Mitchell’s error percentage.

Publisher

IOS Press

Subject

Computational Mathematics,Computer Science Applications,General Engineering

Reference20 articles.

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