Author:
Wang Yawen,Bin Sini,Zhu Shikai,Hu Xiaoting
Publisher
Scientific Research Publishing, Inc.
Reference22 articles.
1. Xu, Y.T., Lyu, Z.G., Huang, Y.G. and Li, X.Y. (2020) Optimization and Implementation of AES Algorithm Based on STM32 MCU. Process Automation Instrumentation, 41, 56-60. https://chn.oversea.cnki.net/KCMS/detail/detail.aspx?dbcode=CJFD&dbname=CJFDLAST2020&filename=ZDYB202007013&uniplatform=OVERSEA&v=FBrazSYzB-bBRjeM4cilrp85xrbI9lm56klGQJewY_FfxAjpFv1g49uZwQfYYS3u
2. Improving overall parallelism in AES accelerator using BRAM and multiple input blocks
3. FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications
4. Implementation of AES S-Boxes using combinational logic
5. Design of AES S-box using combinational logic optimization