Probing charge traps at the 2D semiconductor/dielectric interface-Reference-Cited by-同舟云学术

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Probing charge traps at the 2D semiconductor/dielectric interface

Published:2023 Issue:42 Volume:15 Page:16818-16835
ISSN:2040-3364
Container-title:Nanoscale
language:en
Short-container-title:Nanoscale

Author:

John John Wellington¹^ORCID,Mishra Abhishek¹,Debbarma Rousan¹,Verzhbitskiy Ivan¹^ORCID,Goh Kuan Eng Johnson¹²³^ORCID

Affiliation:

1. Institute of Materials Research and Engineering (IMRE), Agency for Science, Technology and Research (A*STAR), 2 Fusionopolis Way, Innovis #08-03, Singapore 138634, Singapore

2. Division of Physics and Applied Physics, School of Physical and Mathematical Sciences, Nanyang Technological University, 50 Nanyang Avenue 639798, Singapore

3. Department of Physics, National University of Singapore, 2 Science Drive 3, Singapore 117551, Singapore

Abstract

The presence of charge traps at the 2D semiconductor/dielectric interface poses a significant obstacle for device optimisation. Hence, methods to accurately measure and assess these interface traps are in demand.

Funder

Agency for Science, Technology and Research

National Research Foundation Singapore

Publisher

Royal Society of Chemistry (RSC)

Subject

General Materials Science

Link

http://pubs.rsc.org/en/content/articlepdf/2023/NR/D3NR03453D

Reference225 articles.

1. Moore's Law Forever?

2. A. B.Kelleher

3. The chips are down for Moore’s law

4. Recent advances in graphene and other 2D materials

5. A Review of the Synthesis, Properties, and Applications of 2D Materials

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