Oxide and 2D TMD semiconductors for 3D DRAM cell transistors-Reference-Cited by-同舟云学术

Oxide and 2D TMD semiconductors for 3D DRAM cell transistors

Published:2024 Issue:6 Volume:9 Page:934-945
ISSN:2055-6756
Container-title:Nanoscale Horizons
language:en
Short-container-title:Nanoscale Horiz.

Author:

Hur Jae Seok¹^ORCID,Lee Sungsoo²,Moon Jiwon²,Jung Hang-Gyo³,Jeon Jongwook²,Yoon Seong Hun⁴,Park Jin-Hong²⁵^ORCID,Jeong Jae Kyeong¹⁴^ORCID

Affiliation:

1. Department of Electronic Engineering, Hanyang University, Seoul 04763, Republic of Korea

2. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea

3. Department of Semiconductor Convergence Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea

4. Department of Display Science and Engineering, Hanyang University, Seoul 04763, Republic of Korea

5. Advanced Institute of Nano Technology (SAINT), Sungkyunkwan University, Suwon 16419, Republic of Korea

Abstract

2D DRAM scaling has reached its limits. Silicon integration encounters cost and performance challenges, thus prompting exploration of alternative materials. This study examines 3D DRAM structures, compares OSs and TMDs, and evaluates their potential.

Funder

National Research Foundation of Korea

Institute for Information and Communications Technology Promotion

Publisher

Royal Society of Chemistry (RSC)

Link

http://pubs.rsc.org/en/content/articlepdf/2024/NH/D4NH00057A

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