Design of Area efficient comparator architecture using 5T XOR GATE

Abstract

The use of comparators in computation-based designs is extensive, making optimization crucial. While some comparator designs use dynamic logic to achieve low-power consumption, the limitations of low-speed and poor-noise margin make this approach challenging. The proposed comparator design offers a new solution that is both area-efficient and has a high operating speed while consuming low-power. It was designed using 180nm technology in Tanner Tool, and its results were observed. Overall, this work presents a promising new solution for optimizing digital comparators and improving the efficiency and speed of computation-based designs. This work presents a new solution for optimizing N-bit digital comparators in terms of area, power, and speed. The proposed comparator structure is a clever design that consists of two crucial modules - the comparison evaluation module (CEM) and the final module (FM). The CEM is responsible for evaluating the comparison, and it uses a regular structure of repeated logic cells to implement a parallel prefix tree structure. This approach is independent of input operand bit widths, which makes it highly versatile and adaptable to different applications. The FM, on the other hand, validates the final comparison based on the results obtained from the CEM. This ensures that the final output is accurate and reliable. By utilizing these two modules, the proposed comparator structure is able to achieve high-precision comparisons while maintaining a relatively simple and efficient design. Overall, this comparator structure is a promising development in the field of digital circuit design, and it has the potential to improve the performance and reliability of a wide range electronic systems.