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Graphene/Si CMOS Hybrid Hall Integrated Circuits

Published:2014-07-07 Issue:1 Volume:4 Page:
ISSN:2045-2322
Container-title:Scientific Reports
language:en
Short-container-title:Sci Rep

Author:

Huang Le,Xu Huilong,Zhang Zhiyong,Chen Chengying,Jiang Jianhua,Ma Xiaomeng,Chen Bingyan,Li Zishen,Zhong Hua,Peng Lian-Mao

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Link

http://www.nature.com/articles/srep05548.pdf

Reference32 articles.

1. Schwierz, F. Graphene transistor. Nature Nanotechnol. 5, 487–496; 10.1038/nnano.2010.89 (2010).

2. Liao, L. et al. Scalable fabrication of self-aligned graphene transistors and circuits on glass. Nano Lett. 12, 2653–2657; 10.1021/nl201922c (2012).

3. Lin, Y. M. et al. Wafer-scale graphene integrated circuit. Science 332, 1294–1297 (2011).

4. Mueller, T., Xia, F. & Avouris, P. Graphene photodetectors for high-speed optical communications. Nat. Photon. 4, 297–301; 10.1038/nphoton.2010.40 (2010).

5. Eda, G., Fanchini, G. W. & Chhowalla, M. Large-area ultrathin films of reduced graphene oxide as a transparent and flexible electronic material. Nat. Nanotechnol. 3, 270–274; 10.1038/nnano.2008.83 (2008).

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