Double Pinned Perpendicular-Magnetic-Tunnel-Junction Spin-Valve Providing Multi-level Resistance States-Reference-Cited by-同舟云学术

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Double Pinned Perpendicular-Magnetic-Tunnel-Junction Spin-Valve Providing Multi-level Resistance States

Published:2019-08-15 Issue:1 Volume:9 Page:
ISSN:2045-2322
Container-title:Scientific Reports
language:en
Short-container-title:Sci Rep

Author:

Choi Jin-Young,Jun Hansol,Ashiba Kei,Baek Jong-Ung,Shim Tae-Hun,Park Jea-Gun

Funder

National Research Foundation of Korea

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Link

http://www.nature.com/articles/s41598-019-48311-0.pdf

Reference39 articles.

1. Song, Y. J. et al. Highly Functional and Reliable 8Mb STT-MRAM Embedded in 28nm Logic. IEDM, 27.2.1–27.2.4, https://doi.org/10.1109/IEDM.2016.7838491 (2017).

2. Antonyan, A., Pyo, S., Jung, H. & Song, T. Embedded MRAM Macro for eFlash Replacement. IEEE International Symposium on Circuits and Systems (ISCAS), 2–5, https://doi.org/10.1109/ISCAS.2018.8351201 (2018).

3. Jan, G. et al. Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories. Dig. Tech. Pap. - Symp. VLSI Technol. 093008, 8–9, https://doi.org/10.1109/VLSIT.2014.6894357 (2014).

4. Lu, Y. et al. Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications. IEEE Int. Electron Devices Meeting, IEDM, 26.1.1–26.1.4, https://doi.org/10.1109/IEDM.2015.7409770 (2016).

5. Aitken, R. et al. Device and technology implications of the Internet of Things. Symp. VLSI Technol. Dig. Tech. Papers, 1–4, https://doi.org/10.1109/VLSIT.2014.6894339 (2014).

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