An Optimized Pipeline Based Blind Source Separation Architecture for FPGA Applications

Abstract

This work proposes an optimized blind source separation (BSS) architecture utilizing accumulator-based radix 4 multipliers incorporating an independent component analysis (ICA) approach. The signal observed in distinct environmental conditions degraded from its original form. ICA-based filtering is a suitable choice for recovering the desired signal components. Field Programmable Gate Array (FPGA) implementation makes the design much more attractive in high-performance. The proposed BSS-ICA architecture consists of three Random Access Memory (RAM) units and a pipeline-based accumulator radix-4 multiplier. In this work, different source signals such as sinusoidal and speech signals are considered for the analysis. The sources signals are combined with the mixing signal and the resultant signals are processed using the proposed architecture. The pipeline utilized accumulator radix-4 multiplier structure in the proposed design provides good performance in terms of speed and area. The performance of the proposed architecture is analysed using Simulink and FPGA and the results are reported. The speed of the proposed structure is improved by about 19.33% when compared with the conventional design. Likewise, the area (slices) optimization of about 27.27% is achieved for the proposed structure when examined with the existing approach. Hence, the proposed architecture separates the designed signal component with a lesser area and high speed.