Ternary Content-Addressable Memory Based on a Single Two-Dimensional Transistor for Memory-Augmented Learning-Reference-Cited by-同舟云学术

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Ternary Content-Addressable Memory Based on a Single Two-Dimensional Transistor for Memory-Augmented Learning

Published:2024-08-13 Issue:34 Volume:18 Page:23489-23496
ISSN:1936-0851
Container-title:ACS Nano
language:en
Short-container-title:ACS Nano

Author:

Cai Jun¹²^ORCID,Wu Peng³⁴^ORCID,Tripathi Rahul¹²,Kong Jing³⁴^ORCID,Chen Zhihong¹²,Appenzeller Joerg¹²

Affiliation:

1. Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, United States

2. Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907, United States

3. Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, United States

4. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, United States

Funder

Intel Corporation

Semiconductor Research Corporation

Lincoln Laboratory, Massachusetts Institute of Technology

Publisher

American Chemical Society (ACS)

Link

https://pubs.acs.org/doi/pdf/10.1021/acsnano.4c07024

Reference39 articles.

1. Deep learning

2. Efficient Processing of Deep Neural Networks: A Tutorial and Survey

3. Jouppi, N. P.; Young, C.; Patil, N.; Patterson, D.; Agrawal, G.; Bajwa, R.; Bates, S.; Bhatia, S.; Boden, N.; Borchers, A.; In-datacenter performance analysis of a tensor processing unit. In Proceedings of the 44th annual international symposium on computer architecture; ISCA, 2017, pp 1–12.10.1145/3140659.3080246.

4. Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects

5. Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey

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