Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping-Reference-Cited by-同舟云学术

Toward High-Performance p-Type Two-Dimensional Field Effect Transistors: Contact Engineering, Scaling, and Doping

Published:2023-10-09 Issue:20 Volume:17 Page:19709-19723
ISSN:1936-0851
Container-title:ACS Nano
language:en
Short-container-title:ACS Nano

Author:

Oberoi Aaryan¹,Han Ying¹,Stepanoff Sergei P.²³,Pannone Andrew¹,Sun Yongwen¹,Lin Yu-Chuan²⁴,Chen Chen⁵,Shallenberger Jeffrey R.⁶,Zhou Da⁷^ORCID,Terrones Mauricio²⁷⁸^ORCID,Redwing Joan M.²⁵⁹^ORCID,Robinson Joshua A.¹²⁵⁷⁸,Wolfe Douglas E.¹²³,Yang Yang¹^ORCID,Das Saptarshi¹²⁹^ORCID

Affiliation:

1. Department of Engineering Science and Mechanics, Penn State University, University Park, Pennsylvania 16802, United States

2. Department of Materials Science and Engineering, Penn State University, University Park, Pennsylvania 16802, United States

3. Applied Research Laboratory, Penn State University, University Park, Pennsylvania 16802, United States

4. Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, 1001 University Road, Hsinchu City 300093, Taiwan

5. 2D Crystal Consortium Materials Innovation Platform, Penn State University, University Park, Pennsylvania 16802, United States

6. Materials Characterization Laboratory, Penn State University, University Park, Pennsylvania 16802, United States

7. Department of Physics, Penn State University, University Park, Pennsylvania 16802, United States

8. Department of Chemistry, Penn State University, University Park, Pennsylvania 16802, United States

9. Department of Electrical Engineering, Penn State University, University Park, Pennsylvania 16802, United States

Funder

Defense Threat Reduction Agency

National Science Foundation

Publisher

American Chemical Society (ACS)

Subject

General Physics and Astronomy,General Engineering,General Materials Science

Link

https://pubs.acs.org/doi/pdf/10.1021/acsnano.3c03060

Reference64 articles.

1. CMOS Scaling Trends and Beyond

2. DERBYSHIRE, K. Moving to Gaa Fets. https://semiengineering.com/moving-to-gaa-fets/ (accessed 10/21).

3. LAPEDUS, M. What’s the Right Path for Scaling? https://semiengineering.com/whats-the-right-path-for-scaling/ (accessed 10/21).

4. Device scaling limits of Si MOSFETs and their application dependencies

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