Eliminating Ferroelectric Hysteresis in All-Two-Dimensional Gate-Stack Negative-Capacitance Transistors-Reference-Cited by-同舟云学术

Eliminating Ferroelectric Hysteresis in All-Two-Dimensional Gate-Stack Negative-Capacitance Transistors

Published:2023-09-18 Issue:38 Volume:15 Page:45076-45082
ISSN:1944-8244
Container-title:ACS Applied Materials & Interfaces
language:en
Short-container-title:ACS Appl. Mater. Interfaces

Author:

Quan Hui¹²,Meng Dehuan²,Ma Xuezhou²,Qiu Chenguang²^ORCID

Affiliation:

1. Hunan Institute of Advanced Sensing and Information Technology, Xiangtan University, Xiangtan 411105, China

2. Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing 100871, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Publisher

American Chemical Society (ACS)

Subject

General Materials Science

Link

https://pubs.acs.org/doi/pdf/10.1021/acsami.3c06161

Reference39 articles.

1. Steep-slope hysteresis-free negative capacitance MoS2 transistors

2. Steep-Slope WSe2 Negative Capacitance Field-Effect Transistor

3. Is negative capacitance FET a steep-slope logic switch?

4. Sustained Sub-60 mV/decade Switching via the Negative Capacitance Effect in MoS2 Transistors

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