A Simulation Study on Reducing the Grain Boundary Position Dependency in Tunneling Thin-Film Transistors Using a Wide Tunneling Area

Abstract

In this paper, we confirmed the effect of the grain boundary position dependency on short channel poly-Si Tunneling TFTs using technology computer aided design (TCAD) simulation. The simulation results show that the grain boundary (GB) in the channel affects the tunneling barrier and thus, produces variations in the electrical characteristics of the device such as the Vth and off-current. In the case of tunneling TFTs, the characteristics of the entire device are determined by the band to band tunneling (BTBT) currents occurring in very limited regions. In this study, we proposed that a TFT device requires a wider BTBT region because this limited region worsens the variations in the electrical characteristics of the TFT device. Two additional methods were proposed, one using vertical BTBT over a wide area through an additional poly-Si layer deposition and one widening the BTBT area through tilting implantation without an additional deposition process. The simulation results show that the variation of Vth is reduced to 10% through the extension of the BTBT area.