Effects of Plasma Damage Removal on Direct Contact Resistance and Hot-Electron-Induced Punch Through (HEIP) of PMOSFETs

Abstract

In order to reduce contact resistance (Rc) of the source/drain region in nanoscale devices, it is essential to overcome the increasing leakage and hot-electron-induced punch through (HEIP) degradation. In this paper, we propose a simple in situ Si soft treatment technique immediately after direct contact (DC) etching to reduce Rc and minimize HEIP degradation. We found by analysis with a transmission electron microscope, that 10 s of treatment reduced the plasma damaged layer by 19%, which resulted in 10.5% reduction of the P+ contact resistance. For comparison, the P + Rc was reduced by 6.5% when the doping level of the plug implantation was increased by 25%, but the HEIP breakdown voltage (VHEIP) by AC stress was greatly reduced by more than 80 mV, increasing the standby leakage current of DRAM devices. In the case of removing the plasma damage layer, not only did VHIEP not decrease until after 10 s, but also the reduction in Rc was larger than with the plug enhancement. The effect of the plasma damaged layer on HEIP was verified through the plug effect and gate induced drain leakage measurement, based on the distance between the gate and DC for each process. This simple in situ technique not only removed byproducts and the plasma damaged amorphous layer, but it also affected the effective implantation of dopants in subsequent plug processes. It was also cost effective because the process time was short and no extra process steps were added.