Core Insulator Nanosheet Transistor and Structure Optimization to Improve Gate Electrostatic Characteristics

Abstract

This paper proposes the core insulator nano-sheet transistor structure for improved electrostatic characteristics by adding an oxidation process to the conventional Nano-sheet field effect transistor process. The additional insulated core improves the drain induced barrier lowering and the subthreshold slope properties by enhancing the gate controllability. The major advantage of the proposed structure is that it can be fabricated using the conventional nano-sheet field effect transistor process by simply adding another oxidation step. We compared the performance of our proposed device to that of FinFET and nano-sheet field effect transistor at sub 3 nm node using technology computer-aided design simulation. An optimal device structure including the oxide thickness and channel stacking is suggested with consideration for drive current, leakage and electrostatic characteristics.