The Integration Solution of Copper Barrier Deposition for Nanometer Interconnect Process

Abstract

As the dimensions of devices are shrunk quickly, the requirements of metallization become more critical. For VIA barrier and seeding layer filling and deposition, the process was mostly applied with the copper physical vapor deposition methodology in the back-end of line flow of the interconnection metallization. The criteria for barrier and seeding layer deposition are the metal continuity inside the VIA feature and grain size and orientation control for film diffusion barrier and qualities. Besides, while the interconnection size shrunk to nano-scale, the barrier thickness would be very thinner to maintain the VIA resistance; however, it would face the film conformity and continuity consistence within the wafer and different features. The integration solution would be developed and studied with the re-sputter process step adding into the convectional physical vapor deposition process. The resputter process step could not only improve the film conformity and continuity in the VIA's sidewall; but also reduce the resistance of VIA feature over 20%. The improvement of the resputter method adding into the deposition process would be contributed to the standard barrier deposition in the nano-scale feature of the interconnect. Besides, we also discussed the effect of the film properties after the resputter process introduced into the barrier deposition.