Two-Silicon-Nanocrystal Layer Memory Structure with Improved Retention Characteristics

Abstract

It was demonstrated in the literature that the use of self-aligned doubly-stacked Si dots improves retention characteristics of a nanocrystal memory. In this paper, we show that a similar effect may be obtained by using two distinct layers of silicon nanocrystals within the gate dielectric of the MOS structure, if the nanocrystal density in each layer is high enough (above 1012 dots/cm2) so as to get an average effect of at least one smaller dot underneath each larger one. The relative distance of the layers and their position from the silicon substrate and the gate metal are critical for optimum memory operation. Two different double-nanocrystal-layer structures were investigated. In the first structure the two nanocrystal layers were close together and they were composed of dots of different size (lower layer: 3 nm, upper layer: 5 nm), while in the second structure the dot layers were composed of dots of equal diameter (d = 3 nm) and their inter-distance was much larger. In both cases, the retention characteristics of the structure were improved compared with a single dot layer structure. In the second case this improvement was significantly larger than in the first case. Extrapolation of the data to ten years memory operation, showed that the charge loss after this time was only ≈ 12%.