Study on Carrier Mobility Model for PD-Ge Monolithic Optoelectronic Integration Chips

Abstract

Based on the difference of thermal expansion coefficient between Si and Ge, low-intensity tensile stress can be introduced into Ge epitaxial layer on Si substrate. S-Ge/Si semiconductor (as known as low tensile strained Ge grown on Si substrate) has a higher carrier mobility when compared with unstrained-Ge or Si material, so that s-Ge/Si is appropriate for the production of high-speed circuit. At the same time, transformation from indirect bandgap semiconductor Ge into Pseudo-Direct bandgap semiconductor (which is also called PD-Ge) will be happen after s-Ge/Si is heavy doped, which makes LED produced of PD-Ge material perform a higher luminous efficiency because the radiative recombining probability of carriers in PD-Ge material is greatly improved compared with unstrained one. Taking the advantages referred of s-Ge/Si into account, s-Ge/Si has the potential to PD-Ge monolithic optoelectronic integration. Carrier mobility of the semiconductor is one of the key physical parameters during the design and simulation of PD-Ge monolithic optoelectronic integrated system. While as far as the authors are aware, carrier mobility model of s-Ge/Si is still rarely reported to date. In view of that all above, based on the E-k relation in both conduction band and valence band of s-Ge/Si material, the analytical models of physical parameters in energy band are established, and the models are verified by experiments. Then the s-Ge/Si carrier models are further established based on our band structure model, and the Monte Carlo method is used to verify our s-Ge/Si carrier mobility model. The quantificational results of our paper will help understand s-Ge/Si material physics and provide an important theoretical basis for the design of PD-Ge monolithic optoelectronic integration.