Design and Verification of High Performance Standard Cells for Clock Network Applications

Abstract

Standard cell libraries are required by all CAD tools for chip planning. Standard cell libraries contain primitive cells required for advanced configuration. Be that as it may, more crucial cells that have been infrequently upgraded can likewise be incorporated. The principle reason for the CAD tools is to actualize the alleged RTL- to-GDS stream. Design and verification of standard cells (clock path) the advanced clock buffers and inverters present superior performance compared to the existed clock buffers and inverters. The RTL synthesis report shows that timing slack, numbers of inverters and power consumption have been reduced by 65.9%, 80.5% and 5.1% respectively.