Affiliation:
1. Graduate School of Nano IT Design Fusion, Seoul National University of Science and Technology, Seoul, 01811, Republic of Korea
2. Department of Manufacturing Systems and Design Engineering, Seoul National University of Science and Technology, Seoul, 01811, Republic of Korea
Abstract
Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing
demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior
of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm.
At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was
reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when
probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used.
This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.
Publisher
American Scientific Publishers
Subject
Condensed Matter Physics,General Materials Science,Biomedical Engineering,General Chemistry,Bioengineering
Cited by
1 articles.
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