Author:
Hsu Frank F.,Patel Janak H.
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Cited by
2 articles.
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1. A synthesis for testability scheme for finite state machines using clock control;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1999
2. Synthesis of sequential circuits with clock control to improve testability;Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)