High Speed FPGA Implementation of FIR Filter for DSP Applications
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Publisher
IACSIT Press
Link
http://www.ijmo.org/papers/242-S4002.pdf
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. FPGA implementation of power-lite Volterra-inspired neural network equalizer in 180-Gb/s net bitrate IMDD short-reach optical system;Optics Letters;2024-08-08
2. FPGA Implementation of Power-Lite Volterra- Inspired Neural Network Equalizer in 100G PON;Journal of Lightwave Technology;2024-05-01
3. FPGA based realization of a High-Speed 8-Tap FIR Filter for Signal Processing Applications;2023 4th IEEE Global Conference for Advancement in Technology (GCAT);2023-10-06
4. Real-Time Deployment of Simplified Volterra Nonlinear Equalizer in High-Speed PON;IEEE Photonics Technology Letters;2023-10-01
5. Comparative Analysis of Parallel and Cascaded Architectures for the Realization of High-Speed FIR Filters with FPGA;2023 5th International Conference on Inventive Research in Computing Applications (ICIRCA);2023-08-03
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