Analog Electronic Circuit Synthesis Using Simulated Annealing and Geometric Circuit Evolution
Author:
Affiliation:
1. Universidade Federal de Uberlândia, Brazil
Publisher
FapUNIFESP (SciELO)
Subject
Electrical and Electronic Engineering
Link
http://www.scielo.br/scielo.php?script=sci_pdf&pid=S2179-10742023000100013&tlng=en
Reference20 articles.
1. “Automated topology synthesis of analog and RF integrated circuits: A survey,”;Sorkhabi S. E.;Integration - the VLSI Journal,2017
2. “OASYS: a framework for analog circuit synthesis,”;Harjani R.;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1989
3. “OPASYN: a compiler for CMOS operational amplifiers,”;Koh H.;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1990
4. “Three learning methods for reasoning-based synthesis of novel analog circuits,”;Jiao F.;2016 IEEE International Symposium on Circuits and Systems (ISCAS),2016
5. “FEATS: Framework for explorative analog topology synthesis,”;Meissner M.;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2015
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