High Performance Polycrystalline Silicon Thin Film Devices

Abstract

AbstractThe goal of this work was to produce a fabrication process for high performance polycrystalline silicon thin film MOS devices. We have fabricated p-channel devices with mobilities of 35 cm2/V-sec and n-channel devices with mobilities of 50 cm2/V-sec by tailoring the process for depositon of the channel layer, by gate oxidation of the channel at high temperature, and by use of plasma hydrogenation. Under optimal conditions deduced from the study, device threshold voltages are close to zero. Leakage currents in the off-state are less than 0.1 pA/µm of channel length. Fabrication of the devices requires four mask levels and employs standard process steps. Therefore, polycrystalline silicon devices are attractive candidates for a variety of electronics applications, including thin film logic over large area.