Evidence of Energy Relaxation of Charged Defects in Amorphous Silicon Via Forward Bias Capacitance Measurements

Abstract

ABSTRACTIn this paper we show that the usual behaviour of forward bias C-V-f measurements performed on p-i-n structure, Modifies at the lowest test frequencies when the measurement is performed at high temperature (120°C), or if the cell under test is at a certain stage of the degradation process. We relate the effect to the relaxation of charged defects toward dangling bonds in the i-layer of a p-i-n structure. In capacitance measurements under forward bias, the applied sinusoidal test voltage periodically changes the density of injected charge and the defect occupancy in the intrinsic layer. We show that this effect may Modulate the tendency of defects to relax to lower energy configuration. Relaxation changes the time scale of the subsequent thermal emission of the trapped charge; this reflects on the measured capacitance which drops at low frequency. We also demonstrate the possibility to obtain the relaxation parameters from the frequency dependence of the measured capacitance.