Planarized Copper Multilevel Interconnections for ULSI Applications

Abstract

As the degree of large-scale integration (LSI) increases, the area of a single transistor will diminish and the density of transistors will increase. Accordingly, technology for high-density wiring to interconnect the huge number of transistors is needed because transistors cannot perform any useful functions without interconnects and electrodes. For advanced microprocessor chips with a sub-half-micron design rule and at least four interconnect layers, the minimum width of the interconnects becomes less than 0.35 μm.Aluminum or an aluminum alloy is now generally used as the interconnect material in LSI circuits because the physical and chemical properties of aluminum are compatible with current LSI processing: Aluminum forms a thin protective oxide film that withstands various thermal processes; it has relatively low electrical resistivity and halide compounds with a relatively high vapor pressure which are suitable for reactive ion etching (RIE), and it is an inexpensive material. The reliability of aluminum interconnects, however, is a major concern for maintaining the total reliability of advanced LSI. Because of its relatively low melting point, aluminum as an interconnect material is susceptible to stress- and electromigration, which leads to open failure of the interconnect. It is well-known that these failure modes are accelerated by decreasing the width and thickness of the interconnects. Hence, use of aluminum interconnects may be limited for future sub-half-micron LSIs.