S/D Engineering for Sub-100 nm MOSFET using Ultra Shallow Junction Formation Technique, Elevated S/D Structure and SALICIDE Technique

Abstract

AbstractSuppression of short channel effect (SCE) by utilizing the technology of formation of ultrashallow junctions is one of the important issues. The annealing process of implantation-damage that induces transient enhanced diffusion during a subsequent thermal process, such as low-pressure chemical vapor deposition (LPCVD) for gate sidewall spacer, should be optimized. To pursuit high performance of MOSFETs, parasitic resistance must be reduced with scaling. On the other hand, it is difficult to decrease the parasitic resistance in the region of contact junction, which is a function of physical constant such as Schottky barrier height of silicide materials and solid solubility of dopant. The elevated source/drain structure reduces parasitic resistance of contact junction due to reduction of resistance of diffusion beneath salicide materials. Cobalt salicide is widely used till 100nm node. However, cobalt salicide has disadvantage in the thermal budget for shallow junction and quantity of silicon consumption during silicidation. Nickel salicide is one of the candidates for successor of cobalt salicide to 70 nm node or above, because of its characteristics of low temperature formation, low silicon consumption and low contact resistivity on p+ junctions. In this paper, S/D engineering will be discussed from the viewpoint of the process integration of sub-100 nm physical gate length complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) device.