Thermal Modeling of Plastic Ic Packages

Abstract

AbstractThe successful design of plastic integrated circuit packages for high performance VLSI chips is a crucial element in the development of costeffective packaging technology. Unfortunately, however, most common plastic encapsulating and die-bonding materials provide relatively low thermal conductivities and large thermal expansion coefficients, as well as low mechanical strengths and a limited operating temperature range. These material properties combine to produce a large number of thermally induced package failure modes. Thus, insightful material selection and detailed design, based on extensive thermal modeling/analysis, must be performed to achieve acceptable levels of component reliability.This paper begins with a discussion of the temporal development of the temperature fields inside a plastic IC package and continues with the presentation of transient and steady-state, first-order analytical models for: the chip temperature, the temperature and gradient across the die bond, and the half-thickness encapsulant temperature. The values obtained for a typical PDIP package are discussed and compared to the results of a finite-element analysis of this package. The insights obtained from these analyses are used to develop material Figures-of-Merit that can be used in the selection of die-bond and encapsulant materials for plastic IC packages.