Study of Transport Through Low-Temperature GaAs Surface Insulator Layers

Abstract

ABSTRACTSince epilayers of GaAs grown at low substrate temperature (LTGaAs) and annealed at 600°C were first demonstrated to be an effective buffer layer for eliminating backgating effects, the material properties and electronic characteristics of bulk LTGaAs have been actively investigated. Less attention has been paid to thin layers of LTGaAs (∼2000Å), although these have been shown to improve gate-to-drain breakdown characteristics when incorporated as the surface insulator layer in GaAs MISFET's. In bulk LTGaAs that has been annealed for 10 minutes at 600°C, the formation of arsenic precipitates with a density of 1018 cm-3 has been observed. These are considered to be at least partially responsible for the high resistivity of LTGaAs2. While the exact mechanism of precipitate formation is currently unknown, it would seem reasonable to expect the availability of the growth surface to have a significant effect on any defect redistribution during the anneal. This surface effect would become increasingly apparent as the LTGaAs layer thickness was decreased. It is desirable for MISFET applications that the LTGaAs gate insulator layer be as thin as possible, whilst maintaining high breakdown, in order to maximize device transconductance. To achieve this, it is important to understand how the observed bulk features (such as ∼60Å size arsenic precipitates) are affected in thin LTGaAs layers