Integration Challenges for CMP of Copper

Abstract

AbstractAs the minimum feature size of microelectronic devices shrinks down to 130 nm, copper has been successfully adopted into logic applications.1–3 Copper requires damascene processing, which involves etching features into a dielectric substrate, filling the features with metal, and removing any excess metal. Therefore, chemical—mechanical planarization (CMP) is a key process in the final definition of the inlaid copper wires on a circuit. A second advance in the back-end processing of copper is the changing of the dielectric from SiO2 to a Low-κ material, which allows a thicker layer of dielectric to be used. Low-k dielectric films have much lower mechanical properties than SiO2; consequently, this poses new challenges in developing integration schemes.1,3–8