Buried Oxide Soi: Materials, Devices, and VLSI Circuits

Author:

Chen C.-E. Daniel,Team Rad-Hard Soi Project

Abstract

AbstractIn the past couple of years, buried oxide SOI has emerged as the leading SOI approach. Significant advances have been made in the understanding and the preparation of the buried oxide substrates. Various VLSI circuits have been demonstrated with excellent results, proving the maturity and the manufacturability of this technology. In this paper, buried oxide material properties, device parameters and the implementation of a 2.5 urn 4K SRAM and a 1.25 pm 16K SRAM on the buried oxide substrates are reviewed.

Publisher

Springer Science and Business Media LLC

Subject

General Engineering

Reference18 articles.

1. 16 Margail J. , LETI (private communication).

2. 1 Chen C.-E. and Chatterjee P. , presented at the 34th National Symposium of the American Vacuum Society, Anaheim, CA, November, 1987, and to be published in Deposition and Growth: Limits for Microelectronics, edited by G. W. Rubloff (AIP Conference Proceeding, American Vacuum Society Series)

3. 15 Hill D. , Fraundorf P. , and Fraundorf G. , to be published in J. Appl. Phys. Also, this work has been repeated, and expanded at Texas Instruments.

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