Processing damage and electrical performance of porous dielectrics in narrow spaced interconnects

Abstract

AbstractThe damage induced in the low-k material upon exposure to dry etch and ash plasmas is a point of major concern in terms of preservation of the dielectric properties. There is urgent need to assess, classify and quantify the extent of such damage to allow the optimization of patterning processes and conditions. Meander-fork structures with spacings between 250nm and 70nm are used in this study as vehicle to compare trends in electrical performance for different dielectrics: SiO2 and two SiOC:H low-k materials with pristine k values of 3.0 and 2.6. Here we demonstrate that the ‘electrical equivalent damage’ model is a valid and precise methodology for assessing dielectric damage upon processing from interline capacitance evaluation. This analysis allows to distinguish between bulk and sidewall modification and to quantify the extent of damage. Moreover, it provides an interpretation for the degradation of leakage current and breakdown field of the interline dielectric, revealing different trends whether due to only sidewall or total damage.