Comparison of Line Stress Predictions with Measured Electromigration Failure Times

Abstract

AbstractReliability of today's interconnect lines in microelectronic devices is critical to product lifetime. The metal interconnects are carriers of large current densities and mechanical stresses, which can cause void formation or metal extrusion into the passivation leading to failure. The modeling and simulation of stress evolution caused by electromigration in interconnect lines and vias can provide a means for predicting the time to failure of the device. A tool was developed using MathCAD for simulation of electromigration-induced stress in VLSI interconnect structures using a model of electromigration induced stress. This model solves the equations governing atomic diffusion and stress evolution in one dimension. A numerical solution scheme has been implemented to calculate the atomic fluxes and the evolution of mechanical stress in interconnects. The effects of line geometries and overhangs, material properties and electromigration stress conditions have been included in the simulation. The tool has been used to simulate electromigration-induced stress in pure Cu interconnects and a comparison of line stress predictions with measured electromigration failure times is studied. Two basic limiting cases were studied to place some bounds on the results. For a lower bound estimate of the stress it was assumed that the interface can be treated like a grain boundary in Cu. For an upper bound estimate it was assumed that the interface can be treated like a free surface of Cu. Existing data from experimental samples with known structure geometries and electromigration failure times were used to compare the electromigration failure times with predicted stress build-up in the interconnect lines.