Structure and Principles of Operation of a Quaternion VLSI Multiplier-Reference-Cited by-同舟云学术

Structure and Principles of Operation of a Quaternion VLSI Multiplier

Published:2024-09-10 Issue:18 Volume:14 Page:8123
ISSN:2076-3417
Container-title:Applied Sciences
language:en
Short-container-title:Applied Sciences

Author:

Cariow Aleksandr¹^ORCID,Naumowicz Mariusz²^ORCID,Handkiewicz Andrzej³^ORCID

Affiliation:

1. Faculty of Computer Science and Information Technology, West Pomeranian University of Technology, 70-310 Szczecin, Poland

2. Faculty of Computing, Poznań University of Technology, ul. Piotrowo 3a, 60-965 Poznań, Poland

3. Faculty of Technology, The Jacob of Paradise University, 66-400 Gorzów Wielkopolski, Poland

Abstract

The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using 130nm technology. The developed scripts in VHDL are available in the GitHub repository.

Funder

Poznan University of Technology

Publisher

MDPI AG

Link

https://www.mdpi.com/2076-3417/14/18/8123/pdf

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