Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †-Reference-Cited by-同舟云学术

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

Published:2018-04-24 Issue:5 Volume:18 Page:1313
ISSN:1424-8220
Container-title:Sensors
language:en
Short-container-title:Sensors

Author:

Nose Atsushi,Yamazaki Tomohiro,Katayama Hironobu,Uehara Shuji,Kobayashi Masatsugu,Shida Sayaka,Odahara Masaki,Takamiya Kenichi,Matsumoto Shizunori,Miyashita Leo,Watanabe Yoshihiro,Izawa Takashi,Muramatsu Yoshinori,Nitta Yoshikazu,Ishikawa Masatoshi

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Biochemistry,Instrumentation,Atomic and Molecular Physics, and Optics,Analytical Chemistry

Link

http://www.mdpi.com/1424-8220/18/5/1313/pdf

Reference21 articles.

1. A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network

2. [Paper] Column-Parallel Architecture for Line-of-Sight Detection Image Sensor Based on Centroid Calculation

3. A 240 × 180 130 dB 3 µs Latency Global Shutter Spatiotemporal Vision Sensor

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