Compensating Circuit to Reduce the Impact of Wire Resistance in a Memristor Crossbar-Based Perceptron Neural Network

Author:

Truong

Abstract

Wire resistance in metal wire is one of the factors that degrade the performance of memristor crossbar circuits. In this paper, an analysis of the impact of wire resistance in a memristor crossbar is performed and a compensating circuit is proposed to reduce the impact of wire resistance in a memristor crossbar-based perceptron neural network. The goal of the analysis is to figure out how wire resistance influences the output voltage of a memristor crossbar. It emerges that the wire resistance on horizontal lines causes the neuron’s output voltage to vary more than the wire resistance on vertical lines. More interesting, the voltage variation caused by wire resistance on horizontal lines increases proportionally to the length of metal wire. The first column has small voltage variation whereas the last column has large voltage variation. In addition, two adjacent columns have almost the same amount of voltage variation. Under these observations, a memristor crossbar-based perceptron neural network with compensating circuit is proposed. The neuron’s outputs of two columns are put into a subtractor circuit to eliminate the voltage variation caused by the wire resistance. The proposed memristor crossbar-based perceptron neural network is trained to recognize the 26 characters. The proposed memristor crossbar shows better recognition rate compared to the previous work when wire resistance is taken into account. The proposed memristor crossbar circuit can maintain the recognition rate as high as 100% when wire resistance is as high as 2.5 Ω. By contrast, the recognition rate of the memristor crossbar without the compensating circuit decreases by 1%, 5%, and 19% when wire resistance is set to be 1.5, 2.0, and 2.5 Ω, respectively.

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-11

3. A Mathematical Analysis of Wire Resistance Problem in Memristor Crossbars;2022 19th International SoC Design Conference (ISOCC);2022-10-19

4. A Mathematical Formulation of the Wire Resistance Problem in Memristor Crossbars;2022 IEEE 22nd International Conference on Nanotechnology (NANO);2022-07-04

5. A Universal, Analog, In-Memory Computing Primitive for Linear Algebra Using Memristors;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-12

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