Affiliation:
1. Department of Electrical Engineering, City University of Hong Kong, Hong Kong, China
2. Hubei Jiu Feng Shan Laboratory, Wuhan 430074, China
Abstract
Contact scaling is a major challenge in nano complementary metal–oxide–semiconductor (CMOS) technology, as the surface roughness, contact size, film thicknesses, and undoped substrate become more problematic as the technology shrinks to the nanometer range. These factors increase the contact resistance and the nonlinearity of the current–voltage characteristics, which could limit the benefits of the further downsizing of CMOS devices. This review discusses issues related to the contact size reduction of nano CMOS technology and the validity of the Schottky junction model at the nanoscale. The difficulties, such as the limited doping level and choices of metal for band alignment, Fermi-level pinning, and van der Waals gap, in achieving transparent ohmic contacts with emerging two-dimensional materials are also examined. Finally, various methods for improving ohmic contacts’ characteristics, such as two-dimensional/metal van der Waals contacts and hybrid contacts, junction doping technology, phase and bandgap modification effects, buffer layers, are highlighted.
Funder
City University of Hong Kong, Hong Kong SAR, China
Hubei JFS Lab, Wuhan, China
Reference109 articles.
1. Burghartz, J.N. (2013). Guide to State-of-the-Art Electron Devices, Wiley and IEEE.
2. Cramming More Components onto Integrated Circuits;Moore;Electronics,1965
3. The road to miniaturization;Wong;Phys. World,2005
4. Design of ion-implanted MOSFET’s with very small physical dimensions;Dennard;IEEE J. Solid-State Circuits,1974
5. (2019, December 30). Semiconductor Industry Association, 2013 International Technology Roadmap for Semiconductors. Available online: https://www.semiconductors.org/resources/2013-international-technology-roadmap-for-semiconductors-itrs/.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献