Analysis of Channel Potential Recovery According to the Back Pattern in 3D NAND Flash Memory
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Published:2023-03-07
Issue:6
Volume:13
Page:3388
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ISSN:2076-3417
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Container-title:Applied Sciences
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language:en
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Short-container-title:Applied Sciences
Author:
Ryu Gyunseok1, Kim Hyunju1, Lee Jihwan1, Kang Myounggon1ORCID
Affiliation:
1. Department of Electronics Engineering, Korea National University of Transportation, Room No. 326, Smart ICT Building, 50 Daehak-ro, Chungju-si 27469, Republic of Korea
Abstract
This study analyzed the recovery of channel potential according to the program states of adjacent cells. When the verify operation ended, and all voltages dropped to 0 V and the decreased potential of the floating channel caused by the down-coupling phenomenon was recovered continuously over time, regardless of the program states of adjacent WLs. The extent of channel potential recovery showed a similar tendency to that of the variation in the electron concentration of the floating channel. The electron–hole pair recombination decreased the electron concentration, resulting in channel potential recovery. When the adjacent WLs were programmed in a low state, additional electron–hole pair recombination and hole diffusion occurred in the floating channel. Therefore, the channel potential recovered quickly when the adjacent WLs programmed in a low state compared to when they programmed in a high state.
Funder
Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT
Subject
Fluid Flow and Transfer Processes,Computer Science Applications,Process Chemistry and Technology,General Engineering,Instrumentation,General Materials Science
Reference32 articles.
1. Three-Dimensional 128 Gb MLC Vertical nand Flash Memory with 24-WL Stacked Layers and 50 MB/s High-Speed Programming;Park;IEEE J. Solid-State Circuits,2015 2. Cheong, W., Yu, G., Kim, J., Park, J., Song, K.-W., Park, K.-T., Cho, S., Oh, H., Lee, D.D., and Choi, J.-H. (2018, January 11–15). A flash memory controller for 15 μs ultra-low-latency SSD using high-speed 3D NAND flash with 3 μs read time. Proceedings of the 2018 IEEE International Solid-State Circuits Conference-(ISSCC), San Francisco, CA, USA. 3. Choi, Y.-J., Suh, K.-D., Koh, Y.-N., Park, J.-W., Lee, K.-J., Cho, Y.-J., and Suh, B.-H. (1996, January 13–15). A high speed programming scheme for multi-level NAND flash memory. Proceedings of the 1996 Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, USA. 4. A multipage cell architecture for high-speed programming multilevel NAND flash memories;Takeuchi;IEEE J. Solid-State Circuits,1998 5. Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD);Takeuchi;IEEE J. Solid-State Circuits,2009
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