Ocelli: Efficient Processing-in-Pixel Array Enabling Edge Inference of Ternary Neural Networks
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Published:2022-10-30
Issue:4
Volume:12
Page:57
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ISSN:2079-9268
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Container-title:Journal of Low Power Electronics and Applications
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language:en
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Short-container-title:JLPEA
Author:
Tabrizchi SepehrORCID, Angizi Shaahin, Roohi Arman
Abstract
Convolutional Neural Networks (CNNs), due to their recent successes, have gained lots of attention in various vision-based applications. They have proven to produce incredible results, especially on big data, that require high processing demands. However, CNN processing demands have limited their usage in embedded edge devices with constrained energy budgets and hardware. This paper proposes an efficient new architecture, namely Ocelli includes a ternary compute pixel (TCP) consisting of a CMOS-based pixel and a compute add-on. The proposed Ocelli architecture offers several features; (I) Because of the compute add-on, TCPs can produce ternary values (i.e., −1, 0, +1) regarding the light intensity as pixels’ inputs; (II) Ocelli realizes analog convolutions enabling low-precision ternary weight neural networks. Since the first layer’s convolution operations are the performance bottleneck of accelerators, Ocelli mitigates the overhead of analog buffers and analog-to-digital converters. Moreover, our design supports a zero-skipping scheme to further power reduction; (III) Ocelli exploits non-volatile magnetic RAMs to store CNN’s weights, which remarkably reduces the static power consumption; and finally, (IV) Ocelli has two modes, including sensing and processing. Once the object is detected, the architecture switches to the typical sensing mode to capture the image. Compared to the conventional pixels, it achieves an average 10% efficiency on its lane detection power consumption compared with existing edge detection algorithms. Moreover, considering different CNN workloads, our design shows more than 23% power efficiency over conventional designs, while it can achieve better accuracy.
Funder
National Science Foundation
Subject
Electrical and Electronic Engineering
Reference27 articles.
1. Hsu, T.H., Chiu, Y.C., Wei, W.C., Lo, Y.C., Lo, C.C., Liu, R.S., Tang, K.T., Chang, M.F., and Hsieh, C.C. (2019, January 7–11). AI edge devices using computing-in-memory and processing-in-sensor: From system to device. Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA. 2. Rastegari, M., Ordonez, V., Redmon, J., and Farhadi, A. (2016, January 8–16). Xnor-net: Imagenet classification using binary convolutional neural networks. Proceedings of the European Conference on Computer Vision, Amsterdam, The Netherlands. 3. Zhu, C., Han, S., Mao, H., and Dally, W.J. (2017, January 24–26). Trained Ternary Quantization. Proceedings of the International Conference on Learning Representations (ICLR) 2017, Toulon, France. 4. Zhou, S., Wu, Y., Ni, Z., Zhou, X., Wen, H., and Zou, Y. (2016). DoReFa-Net: Training low bitwidth convolutional neural networks with low bitwidth gradients. arXiv. 5. Macsen: A processing-in-sensor architecture integrating mac operations into image sensor for ultra-low-power bnn-based intelligent visual perception;Xu;IEEE Trans. Circuits Syst. II Express Briefs,2020
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