Robust Pixel Design Methodologies for a Vertical Avalanche Photodiode (VAPD)-Based CMOS Image Sensor
Author:
Inoue Akito1ORCID, Torazawa Naoki1, Yamada Shota1, Sugiura Yuki1, Ishii Motonori1, Sakata Yusuke1, Kunikyo Taiki1, Tamaru Masaki1, Kasuga Shigetaka1, Yuasa Yusuke1, Kitajima Hiromu1, Koshida Hiroshi1, Kabe Tatsuya1, Usuda Manabu1, Takemoto Masato1, Nose Yugo1, Okino Toru1, Shirono Takashi1, Nakanishi Kentaro1, Hirose Yutaka1ORCID, Koyama Shinzo1, Mori Mitsuyoshi1, Sawada Masayuki1, Odagawa Akihiro1, Tanaka Tsuyoshi1
Affiliation:
1. Panasonic Industry Co., Ltd., 1006, Oaza Kadoma, Kadoma-shi 571-8506, Osaka, Japan
Abstract
We present robust pixel design methodologies for a vertical avalanche photodiode-based CMOS image sensor, taking account of three critical practical factors: (i) “guard-ring-free” pixel isolation layout, (ii) device characteristics “insensitive” to applied voltage and temperature, and (iii) stable operation subject to intense light exposure. The “guard-ring-free” pixel design is established by resolving the tradeoff relationship between electric field concentration and pixel isolation. The effectiveness of the optimization strategy is validated both by simulation and experiment. To realize insensitivity to voltage and temperature variations, a global feedback resistor is shown to effectively suppress variations in device characteristics such as photon detection efficiency and dark count rate. An in-pixel overflow transistor is also introduced to enhance the resistance to strong illumination. The robustness of the fabricated VAPD-CIS is verified by characterization of 122 different chips and through a high-temperature and intense-light-illumination operation test with 5 chips, conducted at 125 °C for 1000 h subject to 940 nm light exposure equivalent to 10 kLux.
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