A Fully Integrated, Power-Efficient, 0.07–2.08 mA, High-Voltage Neural Stimulator in a Standard CMOS Process

Author:

Palomeque-Mangut DavidORCID,Rodríguez-Vázquez ÁngelORCID,Delgado-Restituto ManuelORCID

Abstract

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm2. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

Funder

Office of Naval Research

Ministerio de Ciencia e Innovación

Ministerio de Universidades

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Biochemistry,Instrumentation,Atomic and Molecular Physics, and Optics,Analytical Chemistry

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1. A Two Channels Fully-Programmable Integrated Neurostimulator with a 0.07% Charge Mismatch;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09

2. Multipolar Stimulator for DBS Application with Concurrent Imbalance Compensation;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

3. Design of Electrical Stimulation Circuit in 180 nm/1.8 V Standard CMOS Process;2023 5th Iranian International Conference on Microelectronics (IICM);2023-10-25

4. Low-cost and prototype-friendly method for biocompatible encapsulation of implantable electronics with epoxy overmolding, hermetic feedthroughs and P3HT coating;Scientific Reports;2023-01-30

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