Intermittent-Aware Design Exploration of Systolic Array Using Various Non-Volatile Memory: A Comparative Study
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Published:2024-02-29
Issue:3
Volume:15
Page:343
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ISSN:2072-666X
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Container-title:Micromachines
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language:en
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Short-container-title:Micromachines
Author:
Taheri Nedasadat1ORCID, Tabrizchi Sepehr1ORCID, Roohi Arman1ORCID
Affiliation:
1. School of Computing, University of Nebraska-Lincoln, Lincoln, NE 68588, USA
Abstract
This paper conducts a comprehensive study on intermittent computing within IoT environments, emphasizing the interplay between different dataflows—row, weight, and output—and a variety of non-volatile memory technologies. We then delve into the architectural optimization of these systems using a spatial architecture, namely IDEA, with their processing elements efficiently arranged in a rhythmic pattern, providing enhanced performance in the presence of power failures. This exploration aims to highlight the diverse advantages and potential applications of each combination, offering a comparative perspective. In our findings, using IDEA for the row stationary dataflow with AlexNet on the CIFAR10 dataset, we observe a power efficiency gain of 2.7% and an average reduction of 21% in the required cycles. This study elucidates the potential of different architectural choices in enhancing energy efficiency and performance in IoT systems.
Funder
National Science Foundation
Reference46 articles.
1. Awad, O.M., Mahmoud, M., Edo, I., Zadeh, A.H., Bannon, C., Jayarajan, A., Pekhimenko, G., and Moshovos, A. (2021, January 18–22). FPRaker: A processing element for accelerating neural network training. Proceedings of the MICRO-54: 54th Annual IEEE/ACM MICRO, Virtual. 2. Melchert, J., Feng, K., Donovick, C., Daly, R., Sharma, R., Barrett, C.W., Horowitz, M., Hanrahan, P.M., and Raina, P. (2023, January 25–29). APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis. Proceedings of the 28th ACM ASPLOS, Vancouver, BC, Canada. 3. Maeng, K., and Lucia, B. (2018, January 8–10). Adaptive Dynamic Checkpointing for Safe Efficient Intermittent Computing. Proceedings of the OSDI, Carlsbad, CA, USA. 4. Towards a formal foundation of intermittent computing;Surbatovich;Proc. ACM Program. Lang.,2020 5. A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores;Silva;WSEAS Trans. Comput.,2010
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